A variety of cross connect switch designs have been used to receive N input signals and output N signals corresponding to any combination of the input signals, whether unicast or multicast to various ones of the output terminals.
One prior art design for a cross connect switch using application specific integrated circuit (ASIC) is referred to herein as the “Output Architecture.” In this configuration, the decision regarding which data to output from each of the N output terminals is made at the output of the switch. A separate memory block is provided for each of the N outputs. Each of the N memory blocks has a size F*N, where F is the frame size. Each of the N memory blocks receives a complete copy of all of the N frames received at the N inputs. Each output is controlled to select one of the N frames of F bytes from the data in its respective memory block, and the remaining F*(N−1) bytes in that memory block are discarded. Thus, the memory block for each output wastes F*(N−1) bytes. In total, the switch requires N*(F*N) bytes of memory, from which N*F*(N−1) bytes are wasted. This may be acceptable when N is small, but the total memory requirements become excessive as N becomes large.
An alternative switch design (referred to herein as the “Input Architecture”) moves the decision point to the input stage of the switching ASIC. In the Input Architecture, only F bytes of memory are required at each output. N multiplexers are provided at the input bus, each of which receives the N input frames. Each of the N multiplexers selects the frame to be output by its respective output terminal. No memory is wasted by this design. However, N multiplexers are required, and each must receive all of the inputs. This may be acceptable for small values of N, but the total amount of logic required and the size of the bus to distribute the N*F bytes to each of the N multiplexers become excessive as N becomes large.
An improved cross connect switch is desired.